Electrically Erasable Programmable Read Only Memory (EE PROM) cells are flash memory devices that use floating gate and control gate elements in combination with programming and erasing carried out by Fowler-Nordheim tunneling through a thin dielectric.
Performance factors such as program erase and read speed, cell size and operating voltage are important considerations in EEPROM cell designs.
Employing Fowler-Nordheim (FN) tunneling instead of channel hot carrier injection for programming and erasing reduces power consumption and permits a larger number of cells to be programmed at the same time.
EEPROM cells with Fowler-Nordheim tunneling are described in U.S. Pat. No. 5,045,490 issued Sep. 3, 1991 to Esquivel et al. entitled "METHOD OF MAKING A PLEATED FLOATING GATE TRENCH EPROM". This patent teaches an EPROM device and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls result in lower bit lines resistivity for a given cell density.
U.S. Pat. No. 5,071,782 issued Dec. 10, 1991 to Moru entitled "VERTICAL MEMORY CELL ARRAY AND METHOD OF FABRICATION" discloses a vertical memory cell EEPROM array that uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked - a drain bitline over a source groundline, defining a channel layer in between. In each bitline row, trenches of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source, drain and channel regions adjacent each trench. The array can be made contactless, half-contact or full contact, trading decreased access time for increased cell area.
U.S. Pat. No. 5,057,446, issued Oct. 15, 1991, to Gill et al. entitled "METHOD OF MAKING AN EEPROM WITH IMPROVED CAPACITIVE COUPLING BETWEEN CONTROL GATE AND FLOATING GATE" describes an integrated circuit with improved capacitive coupling is provided, and includes a first conductor, a second conductor, and a third conductor. The second conductor and third conductor are disposed adjacent each other, separated by an insulator region. The first conductor contacts the third conductor and extends across a portion of the third conductor. The first and third conductors are separated by an insulator region. A voltage applied to first conductor and second conductor is capacitively coupled to third conductor.
U.S. Pat. No. 5,055,898, issued Oct. 8, 1991 to Beilstein, Jr., et al. entitled "DRAM MEMORY CELL HAVING A HORIZONTAL SOI TRANSFER DEVICE DISPOSED OVER A BURIED STORAGE NODE AND FABRICATION METHODS THEREFOR" discloses semiconductor memory cell, and methods of fabricating same, that includes a substrate and a plurality of trench capacitors formed at least partially within the substrate and dielectrically isolated therefrom. A silicon-on-insulator region includes a silicon layer that overlies an insulator. The silicon layer is differentiated into a plurality of active device regions, each of which is disposed above one of the electrically conductive regions. Each of the active device regions is coupled to an overlying first electrode, or wordline, for forming a gate node of an access transistor, to a second electrode, or bitline, for forming a source node of the access transistor, and to the underlying trench capacitor for forming a drain node of the access transistor. The wordline includes a pair of opposed, electrically insulating vertical sidewalls, and the source node and the drain node of each of the access transistors are each comprised of an electrical conductor disposed upon one of the vertical sidewalls. The array of memory cells further includes structure for coupling the active device regions to the substrate to reduce or eliminate a floating substrate effect.
U.S. Pat. No. 5,049,956 issued Sep. 17, 1991 to Yoshida et al., entitled "MEMORY CELL STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE" discloses a memory of an EPROM wherein a drain region, a channel region, and a source region are formed in a direction perpendicular to the surface of a semiconductor substrate. A trench is provided, which penetrates the drain region and the channel region and reaches the source region. A floating gate and a control gate are formed in the trench, in a direction perpendicular to the surface of the semiconductor substrate.
U.S. Pat. No. 5,077,232 issued Dec. 31, 1991, to Kim et al. entitled "METHOD OF MAKING STACKED CAPACITOR DRAM CELLS" teach a method for manufacturing a combined stack-trench type capacitor includes forming a trench in the semiconductor substrate. A conductive layer, used as a first electrode, a dielectric film and another conductor layer, used as a second electrode, are deposited successively and continuously in the trench. The two conductive layers and the sandwiched dielectric film are then etched to form a capacitor pattern. An insulating layer is formed along the edge of the capacitor pattern, and then a third conductor layer is formed over the entire structure.
Japanese Patent JP 04-25077 issued Jan. 28, 1992 to Nakanishi entitled "SEMICONDUCTOR NONVOLATILE MEMORY" discloses a thick insulating film formed on a semiconductor substrate in a flash type EEPROM memory cell, and a P-type semiconductor element region is formed through the film. N+ type source and drain regions are so provided through the film as to hold the region therebetween. Further, a gate insulating film of a thin silicon oxide film is formed on the region. A floating gate electrode made of polysilicon is provided through the film. Since a SOI substrate is used as the semiconductor substrate, the semiconductor element forming region is electrically independently floated at each memory cell, and hence a substrate current is prevented.